The present invention relates to a semiconductor device, which includes: a first-surface-channel-type MOSFET with a threshold voltage of a relatively small absolute value; and a second-surface-channel-type MOSFET with a threshold voltage of a relatively large absolute value, and also relates to a method for fabricating the device.
Performance enhancement of an MOS semiconductor device is needed typically in a system LSI, and to realize such an object, miniaturization, increasing the number of devices integrated and lowering operating voltages are required. For this purpose, it is very important to form surface-channel-type MOSFETs of multiple types on a semiconductor chip.
As a semiconductor device including multiple types of surface-channel-type MOSFETs, a device with logic circuits and DRAMs on a semiconductor chip is known. In such a semiconductor device, MOSFETs, which will be formed in a logic circuit block, should enhance their driving power by lowering the threshold voltage and increasing the saturated current value. On the other hand, MOSFETs, which will be formed in a memory cell block of DRAMs, should increase a data retention time by raising the threshold voltage value and minimizing a leakage current.
To reduce the power consumption of a logic circuit, a technique of forming an MTCMOS (Multi-Threshold CMOS) was reported. In the MTCMOS, a power supply terminal of the logic circuit block is connected to a provisional power supply line. And a voltage-regulating transistor is provided between the provisional power supply line and an original power supply line. When a logic circuit should be operated, power is supplied to the logic circuit block through the provisional power supply line by turning the voltage-regulating transistor ON. In this construction, by lowering the threshold voltage of the MOSFETs in the logic circuit block and raising the saturated current value, driving power can be increased. When the logic circuit should not be operated, power consumption of the logic circuit on standby state can be reduced by turning the voltage-regulating transistor OFF. For such a regulating transistor, lower leakage current is required. Thus, its threshold voltage is set relatively high.
As a means for forming multiple types of surface-channel-type MOSFETs with mutually different threshold voltages on a single semiconductor substrate, a technique of making the dopant concentrations in the channel regions different by implanting dopant ions at mutually different doses into the channel regions is known. Specifically, an implant dose is set higher for the channel region of a surface-channel-type MOSFET that should have a relatively high threshold voltage. In that case, since the dopant concentration in the channel region is relatively high, the threshold voltage increases.
Also, in a surface-channel-type MOSFET, a gate insulating film is thinned as a surface-channel-type MOSFET is miniaturized. Thus, to realize a predetermined threshold voltage, the dopant concentration in the channel region tends to increase.
When a surface-channel-type MOSFET with a relatively high threshold voltage is formed, performance degrades, as the dopant concentration in the channel region gets higher.
For example, if the dopant concentration in the channel region is raised, a leakage current flowing through the pn junction might increase. Consequently, if a MOSFET with a heavily doped channel region is used for a memory cell of a DRAM, data retention time might be shortened. Also, a channel region with an increased dopant concentration can increase the scattering of the dopant in the channel region, which results in decrease of carrier mobility.
Moreover, if a MOSFET with the heavily doped channel region is used as a voltage-regulating transistor for an MTCMOS, ON-state current characteristics might degrade (or increase an ON-state resistance). Therefore, the voltage of a provisional power supply line decreases, thus deteriorating the performance of the logic circuit.
It is therefore an object of the present invention to enhance the performance of a surface-channel-type MOSFET with a higher threshold voltage in a semiconductor device including multiple types of surface-channel-type MOSFETs with mutually different threshold voltages.
To achieve this object, an inventive semiconductor device includes: a first-surface-channel-type MOSFET with a threshold voltage of a relatively small absolute value; and a second-surface-channel-type MOSFET with a threshold voltage of a relatively large absolute value. The first-surface-channel-type MOSFET includes: a first gate insulating film formed on a semiconductor substrate; and a first gate electrode, which has been formed out of a polysilicon film over the first gate insulating film. The second-surface-channel-type MOSFET includes: a second gate insulating film formed on the semiconductor substrate; and a second gate electrode, which has been formed out of a refractory metal film over the second gate insulating film. The refractory metal film is made of a refractory metal or a compound thereof.
In the inventive device, the second gate electrode of the second-surface-channel-type MOSFET is made of a refractory metal or a compound thereof that has a work function corresponding to the intermediate level of the energy gap of silicon. Therefore, the second-surface-channel-type MOSFET can have the absolute value of its threshold voltage increased without raising the dopant concentration in the channel region of the second-surface-channel-type MOSFET. As a result, the second-surface-channel-type NMOS transistor can enhance the OFF-state leakage current characteristics and minimize a leakage current flowing through its pn junction. In addition, the transistor can enhance the ON-state current characteristics to reduce the ON-state resistance.
In one embodiment of the present invention, a dopant concentration in the channel region of the second-surface-channel-type MOSFET is preferably lower than a dopant concentration in the channel region of the first-surface-channel-type MOSFET.
In this manner, the OFF-state leakage current characteristics and the ON-state current characteristics of the second-surface-channel-type MOSFET can be further improved.
In another embodiment of the present invention, the first-surface-channel-type MOSFET is preferably formed in a logic circuit block of the semiconductor substrate, and the second-surface-channel-type MOSFET preferably controls power to be supplied to the logic circuit block.
In such an embodiment, the first-surface-channel-type MOSFET formed in the logic circuit block can increase its driving power, because the MOSFET can have the absolute value of its threshold voltage decreased and its saturated current value raised. In addition, the second-surface-channel-type MOSFET that controls the power to be supplied to the logic circuit block can improve its ON-state current characteristics.
In still another embodiment of the present invention, the first-surface-channel-type MOSFET is preferably formed in a logic circuit block of the semiconductor substrate, and the second-surface-channel-type MOSFET is preferably formed in a memory cell block of the semiconductor substrate. And the second gate insulating film is preferably thicker than the first gate insulating film.
In this manner, the second-surface-channel-type MOSFET can enhance its OFF-state leakage current characteristics and therefore extend a pause time (i.e., a period of time for which charge is stored in a single memory cell), which is usually shortened by the leakage current. As a result, the storage characteristics are improved significantly.
An inventive method is a method for fabricating a semiconductor device including: a first-surface-channel-type MOSFET with a threshold voltage of a relatively small absolute value; and a second-surface-channel-type MOSFET with a threshold voltage of a relatively large absolute value. The method includes the steps of: a) introducing a dopant into regions of a semiconductor substrate where first and second gate electrodes will be formed for the first and second-surface-channel-type MOSFETS, respectively; b) depositing a first insulating film and a polysilicon film in this order over the semiconductor substrate; c) patterning the polysilicon film and the first insulating film, thereby forming the first gate electrode and a dummy gate electrode out of the polysilicon film for the first and second-surface-channel-type MOSFETS, respectively, and a first gate insulating film and a dummy gate insulating film out of the first insulating film for the first and second-surface-channel-type MOSFETs, respectively; d) forming sidewalls covering the first gate electrode and the dummy gate electrode, respectively; e) depositing an interlayer dielectric film over the entire surface of the semiconductor substrate and then removing parts of the interlayer dielectric film, which are located over the first gate electrode and the dummy gate electrode, respectively, thereby exposing the first gate electrode and the dummy gate electrode; f) defining a mask pattern, which covers the first gate electrode but exposes the dummy gate electrode, over the interlayer dielectric film and then etching the dummy gate electrode and the dummy insulating film away using the mask pattern, thereby forming a recess inside the sidewall of the dummy gate electrode; g) forming a second gate insulating film for the second-surface-channel-type MOSFET on part of the surface of the semiconductor substrate that has been exposed inside the recess; h) depositing a refractory metal film, which is made of a refractory metal or a compound thereof, over the entire surface of the semiconductor substrate; and i) removing the refractory metal film, except for its part filled in the recess, thereby forming the second gate electrode out of the refractory metal film for the second-surface-channel-type MOSFET.
According to the inventive method, a first gate electrode for a first-surface-channel-type MOSFET is formed out of a polysilicon film. In addition, a second gate electrode for a second-surface-channel-type MOSFET is formed in a recess after a dummy electrode has been removed. The second gate electrode is formed out of a refractory metal film made of a refractory metal or a compound thereof. In this manner, the first-surface-channel-type MOSFET, including the first gate electrode made of the polysilicon film, and the second-surface-channel-type MOSFET, including the second gate electrode made of the refractory metal film, are obtained. Thus, the second-surface-channel-type MOSFET can have the absolute value of its threshold voltage increased without raising the dopant concentration in the channel region of the second-surface-channel-type MOSFET.
Thus, according to the inventive method, it is possible to enhance the OFF-state leakage current characteristics and the ON current characteristics of the second-surface-channel-type NMOS transistor in fabricating the semiconductor device.
In one embodiment of the present invention, the process of introducing a dopant preferably includes the steps of: introducing the dopant at a relatively high concentration into the region of the semiconductor substrate in which the first gate electrode will be formed; and introducing the dopant at a relatively low concentration into the region of the semiconductor substrate in which the second gate electrode will be formed.
In such an embodiment, the dopant concentration in the channel region of the second-surface-channel-type MOSFET is lower than the dopant concentration in the channel region of the first-surface-channel-type MOSFET. As a result, the OFF-state leakage current characteristics and the ON-state current characteristics of the second-surface-channel-type MOSFET are further improved.